CS603(A) Advanced Computer Architecture Unit 2 study material for RGPV CSE 6th Semester. This unit covers instruction set architecture, CISC, RISC, VLIW, memory hierarchy, locality, coherence, interleaved memory organization and backplane bus systems.
Unit 2 explains how processor instruction sets and memory systems are designed. It focuses on CISC, RISC, VLIW architectures, memory hierarchy principles, interleaved memory, bus systems and system-level communication mechanisms.
Learn how processors understand instructions and how instruction set design affects performance.
Compare different processor architectures used in high-performance computing systems.
Study memory hierarchy, interleaving, backplane buses, arbitration and interrupt handling.
Complete syllabus-based topics of ACA Unit 2.
Instruction Set Architecture defines the set of instructions, addressing modes, registers and operations supported by a processor.
Complex Instruction Set Computer architecture uses powerful and complex instructions to perform multiple low-level operations in a single instruction.
Reduced Instruction Set Computer architecture uses simple, fixed-length instructions for faster execution and efficient pipelining.
Very Long Instruction Word architecture combines multiple operations into one long instruction to exploit instruction-level parallelism.
Organization of registers, cache, main memory and secondary storage according to speed, cost and capacity.
Important memory concepts that improve performance and maintain consistency across memory levels.
Planning memory size and organization according to system requirements and performance goals.
Memory is divided into multiple modules so that consecutive memory accesses can be performed faster.
A technique used to increase memory bandwidth by accessing multiple memory modules in parallel.
Memory access is divided into stages so that multiple memory operations can overlap in execution.
Bandwidth measures data transfer capacity, while fault tolerance allows system operation even after failures.
A communication system that connects CPU, memory and I/O modules through a shared bus structure.
Defines bus width, timing, control signals, address lines and data transfer rules.
Protocols that decide how addresses are placed on the bus and how data transfer timing is controlled.
Bus arbitration selects the device that gets bus control, transactions transfer data, and interrupts notify CPU about events.
These questions are useful for 7 marks and 14 marks answers in RGPV exams.
High-priority topics from ACA Unit 2 for RGPV exam preparation.
| Topic | Expected Frequency | Importance |
|---|---|---|
| RISC Architecture | Very High | ⭐⭐⭐⭐⭐ |
| CISC Architecture | Very High | ⭐⭐⭐⭐⭐ |
| RISC vs CISC | Very High | ⭐⭐⭐⭐⭐ |
| VLIW Architecture | High | ⭐⭐⭐⭐⭐ |
| Memory Hierarchy | Very High | ⭐⭐⭐⭐⭐ |
| Locality of Reference | High | ⭐⭐⭐⭐ |
| Interleaved Memory | High | ⭐⭐⭐⭐ |
| Backplane Bus System | Medium | ⭐⭐⭐⭐ |
| Bus Arbitration | Medium | ⭐⭐⭐⭐ |
| Interrupt Mechanism | Medium | ⭐⭐⭐⭐ |
Instruction Set Architecture is the interface between hardware and software. It defines the instructions, registers, addressing modes and operations supported by a processor.
RISC uses simple and fixed-length instructions, while CISC uses complex instructions that can perform multiple operations in a single instruction.
Memory hierarchy improves system performance by placing frequently used data in faster memory levels like cache and registers.
VLIW stands for Very Long Instruction Word. It executes multiple operations in parallel using a single long instruction word.
RISC vs CISC, VLIW architecture, memory hierarchy, locality of reference, interleaved memory and bus arbitration are highly important.
Yes, Unit 2 is very important because processor architecture and memory hierarchy questions are commonly asked in RGPV exams.
RISC, CISC, VLIW, memory hierarchy and bus systems are very important for RGPV exams.
RISC vs CISC, cache hierarchy, locality and bus arbitration are common computer architecture interview topics.
Unit 2 builds the base for understanding pipelining, cache coherence, memory access and modern CPU design.